Data processing system employing indirect character addressing capability



Jan. 28, 1969 D. L. BAHRS ET AL DATA PROCESSING SYSTEM EMPLOYINGINDIRECT CHARACTER ADDRESSING CAPABILITY Filed June 27, 1966 3 T 2 i 2 laI-y-d E 3 O- m i N LU D O Q 95' U) U) E O D 4 Sheet 1 of 1'7 FIG. I

INVE NTORS.

DAVID L.BAHRS JOHN F. COULEUR PHILIP F. GUDENSCHWAGER RICHARD L. RUTHWILLIAM A. SHELLY ATTORNEY Jan. 28, 1969 Filed June 27, 1966 DATAPROCESSING SYSTEM EMPLOYING INDIRECT CHARACTER ADDRESSING CAPABILITYCOMMAND LOGIC D. L. BAHRS ET AL ZX SWITCH YS ADDER Sheet 2 of 17 D0SWITCH ZDI SWITCH ZY SWITCH ZI SWITCH Jan. 28, 1969 D. L. BAHRS ET AL3,425,039

DATA PROCESSING SYSTEM EMPLOYING INDIRECT CHARACTER ADDRESSINGCAPABILITY Filed June 27, 1966 Sheet .5 of 17 Jan. 28, 1969 D. L. BAHRSET AL 3,425,039

DATA PROCESSING SYSTEM EMPLOYING INDIRECT CHARACTER ADDRESSINGCAPABILITY Jan. 28, 1969 D. L. BAHRS ET AL DATA PROCESSING SYSTEMEMPLOYING INDIRECT CHARACTER ADDRESSING CAPABILITY Filed June 27, 1966Sheet 5 of 1'7 ZX SWITCH Y5 ADDER F I G 5 TO DESIGNATED REGISTER ZYSWlTCH ICU. LL33 Z I SWITCH UNIT Jan. 28, 1969 D. L. BAHRS ET AL3,425,039

DATA PROCESSING SYSTEM EMPLOYING INDIRECT CHARACTER ADDRESSINGCAPABILITY Filed June 27, 1966 Sheet Q of 17 START i I (0|) No TO POINTYES A OF HG] INSTRUCTION CONTAINING v- *m ''d (m me DIC YES NO (00) yPLUS THE REGISTER y O LAST INDIRECT CALLED FOR BY id IS YES ADDRESS,Y,OF INDIRECT WORD Y' WORD y PLUS THE REGISTER CALLED FOR BY 1 IS OPERANDADDRESS FROM POINT FETCH INDIRECT WORD B OF FIGS. AT LOCATION Y. STOREND 20 y, fm AND 1d OF INDIRECT WORD Jan. 28, 1969 D. L. BAHRS ET L.3,425,039

DATA cI:EI;OCEISSINCT SYSTEM EMPLOYING INDIRECT ARACTER ADDRESSINGCAPABILI med June 27, 1966 N Sheet '7 br 17 FROM POINT A 0F FIG. 6

1 Run NO sToRE TAG IN cT REGISTER TD INT 0 YES 0F FIG. I!)

sToRE TAG IN CT REGISTER I =1RIIII YES FETCH INDIRECT OF IND'RECT WORDAT LOCATION v SPECIFIED BY y. STORE New TAG woRD PLUS sToRE NEW yn CTREGISTER REGISTER CALLED Id IN OLD m FOR BY NEW td Is NEW INDIRECTADDREss FETCH NEW 0 INDIRECT WORD I (009+ N USING ADDRESS IN FIRsTINDIRECT YES :33? Tim FETCH NEW INDIRECT I N id woRD. sToRE NEW y OFINDIRECT y,I ,1 IN OLD woRD PLUS vm- 'a- REGISTER CALLED FOR BY IdSTCRED IN CT REGISTER IS OPERAND ADDRESS FROM POINT D OF FIGS. IQBZO.

FIG. 7

Jan. 28, 1969 D. 1.. BAHRS ET AL 3,425,039

DATA PROCESSING SYSTEM EMPLOYING INDIRECT CHARACTER ADDRESSINGCAPABILITY Filed June 27, 1966 Sheet 8 of 1? 8 a; 9 N L Q 9 I 9 9 LL L(I) $3 4 3 5 it U Q 0 O 4 g 5 n A E 0- S 8 3 Jan. 28, 1969 o. L. BAHRS TAL 3,425,039

DATA PROCESSING SYSTEM EMPLOYING INDIRECT CHARACTER ADDRESSINGCAPABILITY Filed June 27. 1966 Sheet 9 of 17 w Q I k 3 m 0 c 3 28 5 8 08 E d 50 p z u I o t Y Ryw o p o 8 3 6 N 2 d E 5 N EH 8 D x a b :t

N k. m G o m N g k '6 I g N m I 0m E 2% J 3 PO 1' 4 LU 3- Q'VN 8 Jan.28, 1969 D. BAHRS ET AL 3,425,039

DATA PROCESSING SYSTEM EMPLOYING INDIRECT CHARACTER ADDRESSINGCAPABILITY Filed June 27, 1966 Sheet /0 of 17 o o u o E 3 8 o 0 Lu xFAULT SWITCHES YE AND YO ZEROS Jan. 28, 1969 D. 1.. BAHRS ET AL3,425,039

DATA PROCESSING SYSTEM EMPLOYING INDIRECT CHARACTER ADDRESSINGCAPABILITY Filed June 27, 1966 Sheet of 17 I42 W; F r oacooe 5 l FAULT Ro 1 {I48 2 0 O FAULT ENCODE 5 NUMBER TO AND --v 201 SWITCH (I44 PRIORITY5 LOGIC 5 S l o I50 I37 i FLT FIG. 14

Jan. 28, 1969 D. BAHRS ET AL DATA PROCESSING SYSTEM EMPLOYING INDIRECTFiled June 27, 1966 FROM POINT C OF FIGS. 6,I9&20.

SET FAULT FLIP-FLOP TO INITIATE FAULT ROUTINE CHARACTER ADDRESSINGCAPABILITY YES FETCH INDIRECT WORD AT LOCATION SPECIFIED BY y. STORE NEWy AND TAG m OLD y AND ms.

Sheet IX of 17 TO POINT E OF FIGJT.

YES

FETCH INDIRECT WORD AT LOCATION SPECIFIED BY y. STORE NEW y,I ,Id

IN OLD yJ ,fg.

NEW y IS OPERAND ADDRESS. NEW TAG SPECIFIES BYTE NEW y IS OPERANDADDRESS.

SIZE AND POSITION FIG. I5

END

Jan. 28, 1969 0. L. BAHRS ET 3,425,039

DATA PROCESSING SYSTEM EMPLOYING INDIRECT CHARACTER ADDRESSINGCAPABILITY Sheet b 0117 Filed June 2'7, 1966 .523 Oh t2: 505m! 302mInt-3m On mm 0m robin HN IP53 N Zak-3m X N ax c m c uxw -Tumo his xn) IxN: v .To x-\ Jan. 28, 1969 D. 1.. BAHRS ET AL 3,425,039

DATA PROCESSING SYSTEM EMPLOYING INDIRECT CHARACTER ADDRESSINGCAPABILITY Filed June 27, 1966 Sheet /4 01 1'7 FROM POINT E NO TO POINTF 0F FIG. I5 OF FIG. 19

YES

FETCH INDIRECT WORD AT LOCATION SPECIFIED BY y. INCREASE BYTE POSITIONBY I. DECREASE TALLY BY I.

( TALL@ N9 YES [SET TALLY RUNOUT INDICATOR BIT so I YES YES YESBYTEPOITION= J s e BYTE posmon 4 NO NO CHANGE BYTE POSITION T0 O.INCREASE y OF INDIRECT WORD BY I.

y IN ORIGINAL INDIRECT WORD IS OPERAND ADDRESS. OPERATE ON BYTE POSITIONCONTAINED IN ORIGINAL INDIRECT WORD.

FIG. I7

Jan. 28, 1969 D. L. BAHRS ET AL DATA PROCESSING SYSTEM EMPLOYINGINDIRECT CHARACTER ADDRESSING CAPABILITY Filed June 27, 1966 Sheet /5 of17 NO I. SDIOIOOI 1 ADIIOIIIJ NO FROM POINT F OF FIG. I7 YES FETCHINDIRECT WORD AT LOCATION SPECIFIED BY y. ADD DELTA TO y AND SUBTRACT lFROM TALLY OF INDIRECT WORD.

" TALLY o YES [sET TALLY RUNOUT INDICATOR] STORE MODIFIED INDIRECT WORDINTO LOCATION FROM WHICH IT CAME.

OPERAND ADDRESS IS y OF ORIGINAL INDIRECT WORD.

FIG. I8

TO POINT YES G OF FIG. I9

FETCH INDIRECT WORD AT LOCATION SPECIFIED BY y. SUBTRACT DELTA FROM yAND ADD I TO TALLY OF INDIRECT WORD.

(TALLYE- YES IsET TALLY RUNOUT INDICATOR STORE MODIFIED INDIRECT WORDINTO LOCATION FROM WHICH IT CAME.

OPERAND ADDRESS IS NEW y OF INDIRECT WORD.

Jan. 28, 1969 D, -4 5 ET AL 3,425,039

DATA PROCESSING SYSTEM EMPLOYING INDIRECT CHARACTER ADDRESSINGCAPABILITY Filed June 27, 1966 Sheet 6 of 17 FROM POINT 6 OF TPGPggIT Hor FIG.I8

I =0IIII00I, I IDICIIIOI) YES YES FETCH INDIRECT woao AT FETCH mm m w RDAT LOCATION SPECIFIED BY y. LOCATION SP CIFIE av y.

F l w Lu 0 I EC 0 STORE NEW TAG.

TA LLY- o TALLY- o YES YES SET TALLY RUNOUT INDICATOR] [sET TALLY RUNOUTINDICATOR} STORE MODIFIED INDIRECT worm STORE MODIFIED INDIRECT won gIgaLocATIou mom WHICH IT lcNAT'gE LOCATION FROM WHICHIT OPERAND ADDRESS ISNEW 3' OF INDIRECT WORD.

YES

MODIFIED Y OF INDIRECT WORD PLUS REGISTER CALLED FOR BY I OF INDIRECTWORD IS 0 ERAND ADDRESS.

,YEs I NEW TAG To U REGISTER] c TO POINTC OF FIG. I5

TO POINT 8 OF FIGS FIG. I9

TO POINT 0 OF FIG] Jan. 28, 1969 D. BAHRS ET AL 3,425,039

DATA PROCESSING SYSTEM EMPLOYING INDIRECT CHARACTER ADDRESSINGCAPABILITY Filed June 27, 1966 Sheet /7 of 17 FROM POINT H 0F FIG. 19

id Dunc, no 1 IDCIIIII) YES I FETCH momecr wono AT LDCATION FETCH momscrWORD AT LOCATION SPECIFIED BY y. ADD I TO y mu SPECIFIED av y. ADD T0 yAND SUBTRACT FROM TALLY 0F SUBTRACT FROM TALLY OF momec'r WORD. INDIRECTwono. STORE NEW TAG.

TALLYI 0 TALLY o NO YES YES [SET TALL! nuwouw INDICATOR I SET TALLYRUNOUT INDICATOR J L I r STORE MODIFIED INDIRECT WORD STORE MODIFIEDINDIRECT woao mo LOCATION FROM wmcu IT m'ro LOCATION FROM WHICH IT came.CAME.

I r OPERAND ADDRESS IS y OF NO ORIGINAL momzc'r wono. @3

YES

MODIFIED y OF INDIRECT WORD PLUS REGISTER CALLED FOR BY I OF INDIRECTWORD IS OPERAND ADDRESS.

NEW 1, anon NEW r mm) T0 POINT c OF FIG. as YES YES NEW TAG TO CTREGISTER TO POINT 0 OF FIG. 1

T0 POINT 5 OF FIG. 6

FIG. 20

United States Patent Ofiice 3,425,039 Patented Jan. 28, 1969 3,425,039DATA PROCESSING SYSTEM EMPLOYING INDIRECT CHARACTER ADDRESSINGCAPABILITY David L. Bahrs, Liverpool, N.Y., John F. Couleur, Phoenix,Philip F. Gudenschwager, Scottsdale, and Richard L. Ruth and William A.Shelly, Phoenix, Ariz., assignors to General Electric Company, acorporation of New York Filed June 27, 1966, Ser. No. 560,572 U.S. Cl. Sill-172.5 12 Claims Int. CI. 61111 13/00 ABSTRACT OF THE DISCLOSURE Adata processing system including a data processor and a memory unit isshown. The processor includes means for providing several differenttypes of address modifications.

INTRODUCTION This invention relates generally to data processing systemsand, more particularly, to means for providing memory addresses in adata processing system.

In a data processing system which executes a sequence of instructionwords called a program to process data, it is often desirable to providethe capability of what is generally referred to as indirect addressing.More correctly, it is desirable to provide for address modificationwhich includes indirect addressing. In address modification, aninstruction word, which normally includes an address portion as well asadditional data concerning an operation to be performed, is operativelyemployed with a second type of information item termed an indirect word.These two Words, the instruction word and the indirect word,collectively define the total of an operation to be performed withrespect to an information item stored in the memory. This latterinformation item is normally called an operand.

Address modification permits versatility and flexibility in establishingprograms for a data processing system and greatly eases the problems ofthe programmer. Address modification also facilitates the use of certainfundamental concepts by more than one programmer without the inclusionof a great number of details in each of the programs. Additionally,certain types of address modifications permit the traversal of tables (aseries of storage locations) by the execution of a single commandwithout the necessity of programmer supervision of each individual stepto thus permit what amounts to an automatic search for a specific detailor information item.

Without address modification it is necessary for the programmer to usewhat is sometimes termed an impure procedure. In an impure procedure,the programmer must modify each instruction used. This prohibits, in amultiprocessor system, the use of a single instruction by more than oneprogram. Thus, an impure procedure does not represent an efficientmethod of programming. Additionally, by address modification andindirect addressing, a particular memory location may be preselectedwhich will serve to point to a particular type of function and with thisknowledge the programmer may proceed to write his program knowing thatwhen he needs this particular type of function he need only referencethis preselected location.

While address modification is fairly well developed in the art it hassuffered from lack of versatility in the number of ways of developingaddresses. Accordingly, it is desirable to extend the usefulness ofaddress modification in a data processing system.

It is, therefore, an object of the present invention to provide animproved address modification apparatus in a data processing system.

It is another object of the invention to extend the address modificationcapability of a data processing system.

It is a still further object to provide a data processing systemembodying new and improved means for address development.

Still another object is to provide a data processing system employingaddress modification apparatus to ensure greater versatility to theprogram.

It is a still further object of the present invention to provide a dataprocessing system employing address modification apparatus which permitsan operation defined by a first information item to be performed upon aportion of an operand defined by a second information item.

The foregoing objects are achieved, in accordance with the illustratedembodiment of the present invention by providing an instruction wordwhich includes an address portion and an operation code portion. Theaddress portion of this instruction word is utilized to obtain a secondor indirect word which is brought from the memory unit to the dataprocessing unit of the system. The indirect word includes an addressportion which defines the memory unit storage location of an informationitem and a tag portion which defines a particular part of theinformation item. Upon the bringing of this information item from thememory, the operation specified by the operation code portion of theinstruction word is performed upon the portion of the information itemdefined by the tag of the indirect Word.

DRAWINGS For a better understanding of the invention, reference is madeto the accompanying drawings in which:

FIGURE 1 illustrates the format of a typical instruction word used inthe present invention;

FIGURE 2 is a major block diagram illustrating the data paths in thesystem of the present invention;

FIGURE 3 is a detailed schematic drawing of one of the components shownin FIGURE 2;

FIGURE 4 is a schematic drawing illustrating the manner in which theseveral timing signals used throughout the present invention aregenerated;

FIGURE 5 is a schematic drawing illustrating a por tion of thecomponents shown in FIGURE 2 and further illustrating a portion of thelogic utilized in certain address modifications of the present system;

FIGURE 6 is a flow chart useful in the description of the R and RIaddress modifications;

FIGURE 7 is a flow chart useful in the description of the IR addressmodification;

FIGURE 8 illustrates the format of an indirect word which includes atally portion;

FIGURES 9, l0 and 11 illustrate the various tag variations which arepossible in the indirect word shown in FIGURE 8;

FIGURE 12 is a block diagram illustrating the manner in which Faults areprocessed by the system of the present invention;

FIGURE 13 is a depiction of an instruction word formulated during theprocessing of a Fault and useful in the explanation of FIGURE 12;

FIGURE 14 illustrates in greater detail the processing of Faults and thegeneration of certain signals necessary to this operation;

FIGURE 15 is a flow chart useful in describing the F, CI and I addressmodifications;

FIGURE 16 is a detailed schematic drawing showing the control of dataflow during certain address modifications and useful in explanation andunderstanding of address modifications employing a tally operation;

FIGURE 17 is a flow chart useful in the explanation of the SC addressmodification;

FIGURE 18 is a flow chart useful for describing the AD and SD addressmodifications;

FIGURE 19 is a flow chart useful in the description of the DI and DICaddress modifications; and,

FIGURE 20 is a flow chart useful in the description of the ID and IDCaddress modifications.

ADDRESS MODIFICATION General Before proceeding with a detailedexplanation of the figures, a brief explanation of the manner in whichthis discussion will be presented is believed desirable. In the ensuingdiscussion of the figures, the heavier lines represent the paths of data(e.g., instructions) movement, including multiple line buses, as opposedto the use of lighter lines to represent control signal paths.Additionally, the logic utilized is meant to be representative of thefunction desired and is not to be limited to the specific logic shown.For example, in many situations an AND- gate may be shown having a databus input and a control line input with the output of this gate being adata bus. Such symbology is to represent the gating of the informationon the several lines of that bus by the action of that control signal.

A great number of the components shown throughout the drawings are inthe form of blocks or similar symbology and these are used to representlogic configurations or components which are well-known in the art suchas adders, registers, switches, decoding logic, etc. The details ofthese items which are considered well-known are not shown except whereit is believed desirable for the purposes of more fully understandingthe invention. Additionally, a certain number of logic configurationswhich are indirectly involved in the present application are shown onlyas blocks with a statement of their function. Further details involvingthese blocks and of the total system of which the present invention is apart may be found in copending patent application Data Processing SystemIncluding Plural Memory Controllers, by David L. Bahrs, et al., Ser. No.555,165 filed June 3, 1966 and assigned to the assignee of the presentinvention. It is also to be expressly understood that a system, of thecomplexity of which the present invention comprises a part, will have alarge number of interrelated control signals which, while they areimportant to the functioning of the operation of the total system, donot play a direct, significant part in the operation of the presentinvention. Therefore, in order to present the instant invention in itssimplest and most easily comprehensible form, these signals have beenomitted and only those control signals which contribute directly to thefunctioning of the invention have been included.

In the embodiment of the invention here utilized, for purposes ofexplanation, information items brought from memory; e.g., instructionwords and data words, are thirty-six bit items. FIGURE 1 illustrates atypical instruction word. Referring now specifically to FIGURE 1 it isseen that the most significant half of the word, bits -17, contain theaddress of a particular location in the memory. The next nine bits, bits18-26, comprise the operation code portion of the instruction word. Itis this portion which designates the operation to be performed. Bits 27,28, and 29 are not utilized in the presently being described invention.The last six bits, bits 3035, collectively form what is known as the tagfield or, more simply, the tag and it is this portion which directs theaddress modification and development techniques of the system of thepresent invention. The tag field is further divided into two parts, a rpart, bits 30-31, and a r part, bits 32, 33, 34 and 35. As will be morefully explained hereinafter, the r,,, part specifies which of four typesof address modification is to be utilized while the r part, dependingupon the type of modification, generally specifies the register to beused in the modification or indexing or, in a tallying type ofmodification, specifies the tallying procedure in detail.

Prior to the continuation of the description of the tag portion of theinstruction word and its ramifications upon the operation of the system,it is believed beneficial to present a general description of data flowwithin the system and, more particularly, within the processor of thesystem which actually performs the address development or modification.This flow of data may best be seen with respect to FIGURE 2 whichillustrates only the flow of data between a memory unit and theprocessor and, within the processor, between a major portion of thecomponents which are utilized in the present invention. All componentsshown other than a memory unit 10 are a part of the processor. Memoryunit 10 delivers information items in the form of thirty-six bitinstruction words or data words via a thirty-six bit bus 12 to a ZDIswitch 14. From the ZDI switch 14 incoming information items,hereinafter often collectively referred to as data, may be directedalong one of three paths. The first of these paths is to an M-Register16, a seventy-two bit register capable of holding two words. From theM-Register 16 incoming data or portions thereof may be directed to oneof eight 18 bit Index Registers collectively designated by the referencecharacter 18. The eight Index Registers are individually identified asXg-X7 and the incoming data to these registers is directed to theappropriate ones by means of an input IX switch 20. Data may also passfrom the M-Register 16 to a seventy-two bit accumulator or AQ-Register22. The AQ-Register is further defined as having an A portion 24,hereinafter referred to as the A-Register, and a Q portion 26,hereinafter referred to as the Q-Register.

The second path incoming data may take from the ZDI switch 14 is to aplurality of four registers 28 which are collectively known as theInstruction Registers. The Instruction Registers are comprised of four18 bit registers, namely a YE-Register 30, a COE-Register 32, aYO-Register 34 and a COO-Register 36. As the name implies, theInstruction Registers 28 serve to hold the instructions grought from thememory unit 10. In the normal operation of the presently being describedsystem, instruction words such as those illustrated in FIGURE 1 arebrought from the memory unit 10 in pairs. Under suitable gating, theaddress portion of the first or even instruction of a pair is placed ina YE-Register 30 while the command portion of this even instruction(bits 18-35) is placed into the COB-Register 32. Similarly, the addressportion of the odd instruction of a pair is placed into the YO- Register34, while the command portion of the odd instruction is placed into theCOO-Register 36.

The third path which data entering the processor via the ZDI switch 14may follow is from the ZDI switch to a ZY switch 38 and from there, viabus 40, to a YS adder 42. The contents of the YE and YO-Registers arealso selectively transferred via the ZY switch 38 and bus 40 to the YSadder 42. The YS adder is the control frame general purpose adder and ishighly instrumental in the address modification operation to besubsequently described.

While the transfer of the YE and YO-Registers to the YS adder is thenormal case, in certain situations to be subsequently described thecontents of the YE and Y0- Registers may be transferred via the ZYswitch 38 to the M-Register 16.

The contents of the COE and COO-Registers are selectively transferredvia a 2] switch 44 to one of several places. These contents may betransferred via the Z1 switch to a block 46 designated as Command Logicor to a second block 48 designated as Zone Logic. The Command Logicdecodes the operation code portion (bits 18-26) of the instruction wordand transmits this information to the memory unit 10 to direct theoperation of that unit. The Zone Logic is utilized to inform the memoryunit 10, in certain circumstances, of the manner in which the memoryunit is to process information as the system of the present inventionpossesses the capability of operating on characters or bytes of eithersix or nine bits. For a more complete understanding of the Command Logicand Zone Logic, reference is made to the aforementioned copending patentapplication, Ser. No. 555,165. The tag part of the contents of the COEor COO-Registers (bits 30-35) may be selectively transferred to one orboth of two places. These bits may be transferred to one or both of twoplaces. These bits may be transferred via the Z1 switch 4 to aCT-Register 50 which serves to store the tag part of an instruction wordduring certain types of address modification. The tag part of theinstruction word may also be transmitted to a Tag Decode Logic block 52which includes sufficient circuitry to decode both the t and the 1,,parts of the tag portion of the instruction word to direct the addressmodification as will be more fully explained with respect to FIGURE 3.The capability is also provided for the transfer of information from theCT-Register 50 to the Tag Decode Logic 52 via a bus 54.

In addition to that just described, and as shown in FIG- URE 2, thecontents of the CT-Register 50 may be transmitted via a bus 56 to a ZXswitch 58. The ZX switch 58 has additional inputs from each of the IndexRegisters 18 (X -X and from the AQ-Register 22. The last input to the ZXswitch is from an lCT-Register 60. The ICT- Register 60 is an eighteenbit register which holds the address of the instruction presently beingexecuted by the processor. The ICT-Register receives its input from theYS adder 42.

The output of the ZX switch 58 forms an input to the YS adder 42 and itis thus seen that the YS adder is capable of receiving data via the ZYswitch, the ZX switch, the CT-Register 50 and the ICT-Register 60. Theaddress modifications are performed in the YS adder and once aneffective address (one which is to be used to retrieve a word frommemory) has been formulated in the YS adder, it is transferred to anAddress Register (ADR) 62. From the Address Register 62 the address istransferred via an address bus 64 to the memory unit 10 for theaccessing of the location specified by that address.

The remaining showing of FIGURE 2 concerns a DO switch 63 which receivesdata from the YS adder 42 and the Address Register 62 and transmits thisdata to the memory unit 10 via a thirty-six line bus 65.

TAG FIELD General Bits 3031 Modification type Register"-Indexingaccording to ta as register designator and termination of the addressmodification procedure.

Register, then Indirect"Indexing according to t i as registerdesignator, then substitution and continuation of the modificationprocedure as directed by the tag of this indirect word.

"Indirect, then Registcr"Saving of t; as final register designator, thensubstitution and continuation of the modification procedure as directedby the tag of this indirect word.

Indirect, then Tally"-Substitution, then use of this indirect wordaccording to t as telly designator.

r .-The I part of the tag, bits 32-35, specifies further the action foreach modification type. in the case of the modification types R, R1 andIR, the r part of the tag is called the register designator" andnormally specifies the register to be used in an indexing step. Thefollowing table lists the further action steps possible under one ormore of the modifier types R, RI and IR.

Bit.

Mncmonic Meaning 32 33 34 35 0 0 0 0 N N o modification. 0 0 0 1 AUA-register bits 0-17. 0 0 1 0 QU Q-register bits 0-17. 0 0 l 1 D UDirect upper. 0 I 0 0 ICT Instruction counter. 0 1 0 1 AL A-registerbits 18-35. D 1 l 0 QL Q-register bits 18-35. D 1 1 1 DL Direct lower. 10 (J 0 X0 X-register 0. l 0 0 1 X X-reglster l. 1 0 1 0 X X-reglster 2.1 0 l 1 X X-register 3. 1 l 0 0 X4 X-register 4. 1 l 0 1 X5 X-rcgistor5. 1 1 i 0 XI X-register 6. l 1 1 1 X1 X-register 7.

From the above table it should be noted that there are three exceptionsto the statement that the r designates a register for indexing. Theseexceptions are the mnemonics N, DU and DL. In the case of N, nomodification is effected and the address portion of the instruction wordis the address used to obtain the operand. In the cases of DU and DL theaddress portion of the instruction word serves as the operand and willbe placed, respectively, in the upper or lower half of the registerspecified by the instruction word. It should, however, be pointed out atthis time that DU and DL are permissible only with the R modifier andare not permitted under RI or IR.

In the case of the IT modifier, the i part of the tag is called thetally designator" and usually specifies the tallying in detail. Themodification type IT consists of a substitution and the use of thisindirect word as specified by the r part of the instruction or previousindirect word as tally designator. There are ten variations controlledby the 1 part (bits 32-35) when the 1 part is an IT modifier. Thesevariations are shown in the table below.

crement tally, and continue.

As previously indicated, there are exceptions to the statement that theIT requires a tallying operation in that the variations F, CI and I donot involve tallying. This, however, will be explained in more detailsubsequently in this description.

Tag field decoding-As was stated with respect to FIGURE 2, the tag fieldof an instruction word (bits 30-35) is selectively gated from theappropriate COE- Register 32 or the COO-Register 36 through the Z1switch 44 to the Tag Decode Logic 52, the functional details of whichmay best be seen with respect to FIGURE 3. Referencing now FIGURE 3, itis seen that the Tag Decode Logic 52 may be considered as being dividedinto two parts as indicated by the dotted lines. These two parts are a rdecoding portion 66 and a r decoding portion 68. There are six inputterminals to the Tag Decode Logic 52, designated as T30-T35, tocorrespond respectively with bits 30-35 of the tag field of aninstruction word.

